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| UJA1076 High-speed CAN core system basis chip Rev. 02 -- 27 May 2010 Product data sheet 1. General description The UJA1076 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a high-speed Controller Area Network (CAN). The UJA1076 supports the networking applications used to control power and sensor peripherals by using a high-speed CAN as the main network interface. The core SBC contains the following integrated devices: * High-speed CAN transceiver, inter-operable and downward compatible with CAN transceiver TJA1042, and compatible with the ISO 11898-2 and ISO 11898-5 standards * Advanced independent watchdog (UJA1076/xx/WD versions) * 250 mA voltage regulator for supplying a microcontroller; extendable with external PNP transistor for increased current capability and dissipation distribution * * * * Separate voltage regulator for supplying the on-board CAN transceiver Serial Peripheral Interface (SPI) (full duplex) 2 local wake-up input ports Limp-home output port In addition to the advantages gained from integrating these common ECU functions in a single package, the core SBC offers an intelligent combination of system-specific functions such as: * Advanced low-power concept * Safe and controlled system start-up behavior * Detailed status reporting on system and sub-system levels The UJA1076 is designed to be used in combination with a microcontroller that incorporates a CAN controller. The SBC ensures that the microcontroller always starts up in a controlled manner. NXP Semiconductors UJA1076 High-speed CAN core system basis chip 2. Features and benefits 2.1 General Contains a full set of CAN ECU functions: CAN transceiver Scalable 3.3 V or 5 V voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB Separate voltage regulator for the CAN transceiver (5 V) Watchdog with Window and Timeout modes and on-chip oscillator Serial Peripheral Interface (SPI) for communicating with the microcontroller ECU power management system Designed for automotive applications: Excellent ElectroMagnetic Compatibility (EMC) performance 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) on the CAN bus pins and the wake pins 6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 on the CAN bus pins and the wake pins 58 V short-circuit proof CAN bus pins Battery and CAN bus pins are protected against transients in accordance with ISO 7637-3 Supports remote flash programming via the CAN bus Small 6.1 mm x 11 mm HTSSOP32 package with low thermal resistance Pb-free; RoHS and dark green compliant 2.2 CAN transceiver ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver Dedicated low dropout voltage regulator for the CAN bus: Independent of the microcontroller supply Significantly improves EMC performance Bus connections are truly floating when power is off SPLIT output pin for stabilizing the recessive bus level 2.3 Power management Wake-up via CAN or local wake pins with wake-up source detection 2 wake pins: WAKE1 and WAKE2 inputs can be switched off to reduce current flow Output signal (WBIAS) to bias the wake pins, selectable sampling time of 16 ms or 64 ms Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller Sleep mode with very low sleep current and full wake-up capability UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 2 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 2.4 Control and Diagnostic features Safe and predictable behavior under all conditions Programmable watchdog with independent clock source: Window, Timeout (with optional cyclic wake-up) and Off modes supported (with automatic re-enable in the event of an interrupt) 16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis Global enable output for controlling safety-critical hardware Limp home output (LIMP) for activating application-specific `limp home' hardware in the event of a serious system malfunction Overtemperature shutdown Interrupt output pin; interrupts can be individually configured to signal V1/V2 undervoltage, CAN/local wake-up and cyclic and power-on interrupt events Bidirectional reset pin with variable power-on reset length to support a variety of microcontrollers Software-initiated system reset 2.5 Voltage regulators Main voltage regulator V1: Scalable voltage regulator for the microcontroller, its peripherals and additional external transceivers 2 % accuracy 3.3 V and 5 V versions available Delivers up to 250 mA and can be combined with an external PNP transistor for better heat distribution over the PCB Selectable current threshold at which the external PNP transistor starts to deliver current Undervoltage warning at 90 % of nominal output voltage and undervoltage reset at 90 % or 70 % of nominal output voltage Can operate at VBAT voltages down to 4.5 V (e.g. during cranking), in accordance with ISO7637 pulse 4/4b and ISO16750-2 Stable output under all conditions Voltage regulator V2 for CAN transceiver: Dedicated voltage regulator for on-chip high-speed CAN transceiver Undervoltage warning at 90 % of nominal output voltage Can be switched off; CAN transceiver can be supplied by V1 or by an external voltage regulator Can operate at VBAT voltages down to 5.5 V (e.g. during cranking) in accordance with ISO7637, pulse 4 Stable output under all conditions UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 3 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 3. Ordering information Table 1. Ordering information Package Name UJA1076TW/5V0/WD UJA1076TW/3V3/WD UJA1076TW/5V0 UJA1076TW/3V3 [1] UJA1076TW/5V0xx versions contain a 5 V regulator (V1); UJA1076TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. Type number[1] Description plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad Version SOT549-1 HTSSOP32 4. Block diagram UJA1076 BAT V1 V2 GND V1 UV V2 UV EXT. PNP CTRL VEXCTRL VEXCC WBIAS V1 V2 SCK SDI SDO SCSN WAKE1 WAKE2 WDOFF EN WAKE SYSTEM CONTROLLER INTN RSTN OSC TEMP LIMP V2 HS-CAN CANH CANL TXDC RXDC BAT 015aaa108 SPLIT Fig 1. Block diagram UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 4 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 5. Pinning information 5.1 Pinning i.c. i.c. i.c. V1 i.c. RSTN INTN EN SDI 1 2 3 4 5 6 7 8 9 32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 i.c. 26 i.c. 25 i.c. 24 SPLIT 23 GND 22 CANL 21 CANH 20 V2 19 WAKE2 18 WAKE1 17 LIMP 015aaa109 UJA1076 SDO 10 SCK 11 SCSN 12 TXDC 13 RXDC 14 TEST1 15 WDOFF 16 Fig 2. Pin configuration 5.2 Pin description Table 2. Symbol i.c. i.c. i.c. V1 i.c. RSTN INTN EN SDI SDO SCK SCSN TXDC RXDC TEST1 WDOFF LIMP UJA1076_2 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description internally connected; should be left floating internally connected; should be left floating internally connected; should be left floating voltage regulator output for the microcontroller (5 V or 3.3 V depending on SBC version) internally connected; should be left floating reset input/output to and from the microcontroller interrupt output to the microcontroller enable output SPI data input SPI data output SPI clock input SPI chip select input CAN transmit data input CAN receive data output test pin; pin should be connected to ground WDOFF pin for deactivating the watchdog limp home output All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 5 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Pin description ...continued Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description local wake-up input 1 local wake-up input 2 5 V voltage regulator output for CAN CANH bus line CANL bus line ground CAN bus common mode stabilization output internally connected; should be left floating internally connected; should be left floating internally connected; should be left floating control pin for external wake biasing transistor current measurement for external PNP transistor; this pin is connected to the collector of the external PNP transistor test pin; pin should be connected to ground control pin of the external PNP transistor; this pin is connected to the base of the external PNP transistor battery supply for the SBC Table 2. Symbol WAKE1 WAKE2 V2 CANH CANL GND SPLIT i.c. i.c. i.c. WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND. 6. Functional description The UJA1076 combines the functionality of a high-speed CAN transceiver, two voltage regulators and a watchdog (UJA1076/xx/WD versions) in a single, dedicated chip. It handles the power-up and power-down functionality of the ECU and ensures advanced system reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation of external switches. Additionally, it provides a periodic control signal for pulsed testing of wake-up switches, allowing low-current operation even when the wake-up switches are closed in Standby mode. All transceivers are optimized to be highly flexible with regard to bus topologies. In particular, the high-speed CAN transceiver is optimized to reduce ringing (bus reflections). V1, the main voltage regulator, is designed to power the ECU's microcontroller, its peripherals and additional external transceivers. An external PNP transistor can be added to improve heat distribution. V2 supplies the integrated high-speed CAN transceiver. The watchdog is clocked directly by the on-chip oscillator and can be operated in Window, Timeout and Off modes. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 6 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.1 System Controller 6.1.1 Introduction The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in Figure 3. These modes are discussed in more detail in the following sections. 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (Vth(det)poff). In Off mode, the voltage regulators are disabled and the bus systems are in a high-resistive state. The CAN bus pins are floating in this mode. As soon as the battery supply rises above the power-on detection threshold (Vth(det)pon), the SBC goes to Standby mode, and a system reset is executed (reset pulse width of tw(rst), long or short; see Section 6.5.1 and Table 11). 6.1.3 Standby mode The SBC will enter Standby mode: * From Off mode if VBAT rises above the power-on detection threshold (Vth(det)pon) * From Sleep mode on the occurrence of a CAN or local wake-up event * From Overtemp mode if the chip temperature drops below the overtemperature protection release threshold, Tth(rel)otp * From Normal mode if bit MC is set to 00 or a system reset is performed (see Section 6.5) In Standby mode, V1 is switched on. The CAN transceiver will either be in a low-power state (Lowpower mode; STBCC = 1; see Table 6) with bus wake-up detection enabled or completely switched off (Off mode; STBCC = 0) - see Section 6.7.1. The watchdog can be running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the setting of the watchdog mode control bit (WMC) in the WD_and_Status register (Table 4). The SBC will exit Standby mode if: * Normal mode is selected by setting bits MC to 10 (V2 disabled) or 11 (V2 enabled) * Sleep mode is selected by setting bits MC to 01 * The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the SBC to enter Overtemp mode UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 7 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip from Standby or Normal VBAT below power-off threshold Vth(det)poff (from all modes) Overtemp V1: OFF V2: OFF limp home = LOW (active) CAN: Off and high resistance watchdog: OFF chip temperature above OTP activatrion threshold Tth(act)otp Off V1: OFF V2: OFF CAN: Off and high resistance watchdog: OFF INTN: HIGH chip temperature below OTP release threshold Tth(rel)otp VBAT below power-on threshold Vth(det)pon VBAT above power-on threshold Vth(det)pon watchdog overflow or V1 undervoltage watchdog trigger Standby V1: ON V2: OFF CAN: Lowpower/Off watchdog: Timeout/Off MC = 00 reset event or MC = 00 MC = 10 or MC = 11 MC = 01 and INTN = HIGH and one wake-up enabled and no wake-up pending wake-up event if enabled Normal V1: ON V2: ON/OFF CAN: Active/Lowpower watchdog: Window/ Timeout/Off MC = 1x Sleep V1: OFF V2: OFF CAN: Lowpower/Off watchdog: OFF RSTN: LOW MC = 01 successful watchdog trigger MC = 01 and INTN = HIGH and one wake-up enabled and no wake-up pending 015aaa110 Fig 3. UJA1076 system controller UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 8 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.1.4 Normal mode Normal mode is selected from Standby mode by setting bits MC in the Mode_Control register (Table 5) to 10 (V2 disabled) or 11 (V2 enabled). In Normal mode, the CAN physical layer will be enabled (Active mode; STBCC = 0; see Table 6) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up detection active. The SBC will exit Normal mode if: * * * * Standby mode is selected by setting bits MC to 00 Sleep mode is selected by setting bits MC to 01 A system reset is generated (see Section 6.1.3; the SBC will enter Standby mode) The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the SBC to switch to Overtemp mode 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register (Table 5) to 01. The SBC will enter Sleep mode providing there are no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source is enabled (CAN or WAKE). Any attempt to enter Sleep mode while one of these conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width; see Section 6.5.1 and Table 11). In Sleep mode, V1 and V2 are off and the CAN transceiver will be switched off (Off mode; STBCC = 0; see Table 6) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up detection active - see Section 6.7.1). The watchdog is off and the reset pin is LOW. A CAN or local wake-up event will cause the SBC to switch from Sleep mode to Standby mode, generating a (short or long; see Section 6.5.1) system reset. The value of the mode control bits (MC) will be changed to 00 and V1 will be enabled. 6.1.6 Overtemp mode The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip temperature exceeds the overtemperature protection activation threshold, Tth(act)otp, In Overtemp mode, the voltage regulators are switched off and the bus system is in a high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW. The chip temperature must drop a hysteresis level below the overtemperature shutdown threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the SBC enters Standby mode and a system reset is generated (reset pulse width of tw(rst), long or short; see Section 6.5.1 and Table 11). UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 9 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.2 SPI 6.2.1 Introduction The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave operations. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer: * * * * SCSN: SPI chip select; active LOW SCK: SPI clock; default level is LOW due to low-power concept SDI: SPI data input SDO: SPI data output; floating when pin SCSN is HIGH Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge (see Figure 4). SCS SCK 01 sampled 02 03 04 15 16 SDI X MSB 14 13 12 01 LSB X SDO floating X MSB 14 13 12 01 LSB floating mce634 Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. 000 001 010 011 Register map Write access bit 12 = 0 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only Read/Write access bits 11... 0 WD_and_Status register Mode_Control register Int_Control register Int_Status register Address bits 15, 14 and 13 UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 10 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.2.3 WD_and_Status register Table 4. Bit WD_and_Status register Access Power-on Description default R R/W 000 0 register address access status 0: register set to read/write 1: register set to read only 11 WMC R/W 0 watchdog mode control 0: Normal mode: watchdog in Window mode; Standby mode: watchdog in Timeout mode 1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in Off mode 10:8 NWP[1] R/W 100 nominal watchdog period 000: 8 ms 001: 16 ms 010: 32 ms 011: 64 ms 100: 128 ms 101: 256 ms 110: 1024 ms 111: 4096 ms 7 WOS/SWR R/W watchdog off status/software reset 0: WDOFF pin LOW; watchdog mode determined by bit WMC 1: watchdog disabled due to HIGH level on pin WDOFF; results in software reset 6 V1S R V1 status 0: V1 output voltage above 90 % undervoltage recovery threshold (Vuvr; see Table 10) 1: V1 output voltage below 90 % undervoltage detection threshold (Vuvd; see Table 10) 5 V2S R V2 status 0: V2 output voltage above undervoltage release threshold (Vuvr; see Table 10) 1: V2 output voltage below undervoltage detection threshold (Vuvd; see Table 10) 4 WLS1 R wake-up 1 status 0: WAKE1 input voltage below switching threshold (Vth(sw)) 1: WAKE1 input voltage above switching threshold (Vth(sw)) 3 WLS2 R wake-up 2 status 0: WAKE2 input voltage below switching threshold (Vth(sw)) 1: WAKE2 input voltage above switching threshold (Vth(sw)) 2:0 [1] Symbol 15:13 A2, A1, A0 12 RO reserved R 000 Bit NWP is set to it's default value (100) after a reset. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. UJA1076_2 Product data sheet Rev. 02 -- 27 May 2010 11 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.2.4 Mode_Control register Table 5. Bit 15:13 12 Mode_Control register Symbol Access Power-on default 001 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11:10 MC R/W 00 mode control 00: Standby mode 01: Sleep mode 10: Normal mode; V2 off 11: Normal mode; V2 on 9 LHWC[1] R/W 1 limp home warning control 0: no limp home warning 1: limp home warning is set; next reset will activate LIMP output 8 LHC[2] R/W 0 limp home control 0: LIMP pin set floating 1: LIMP pin driven LOW 7 ENC R/W 0 enable control 0: EN pin driven LOW 1: EN pin driven HIGH in Normal mode 6 5 reserved WBC R R/W 0 0 wake bias control 0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1 1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1 4 PDC R/W 0 power distribution control 0: V1 threshold current for activating the external PNP transistor; load current rising; Ith(act)PNP = 85 mA; V1 threshold current for deactivating the external PNP transistor; load current falling; Ith(deact)PNP = 50 mA; see Figure 7 1: V1 threshold current for activating the external PNP transistor; load current rising; Ith(act)PNP = 50 mA; V1 threshold current for deactivating the external PNP transistor; load current falling; Ith(deact)PNP = 15 mA; see Figure 7 3:0 [1] [2] A2, A1, A0 R RO reserved R 0000 Bit LHWC is set to 1 after a reset. Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 12 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.2.5 Int_Control register Table 6. Bit 15:13 12 Int_Control register Symbol Access Power-on default 010 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11 V1UIE R/W 0 V1 undervoltage interrupt enable 0: V1 undervoltage warning interrupts cannot be requested 1: V1 undervoltage warning interrupts can be requested 10 V2UIE R/W 0 V2 undervoltage interrupt enable 0: V2 undervoltage warning interrupts cannot be requested 1: V2 undervoltage warning interrupts can be requested 9:8 7:6 reserved WIC1 R R/W 00 00 wake-up interrupt 1 control 00: wake-up interrupt 1 disabled 01: wake-up interrupt 1 on rising edge 10: wake-up interrupt 1 on falling edge 11: wake-up interrupt 1 on both edges 5:4 WIC2 R/W 00 wake-up interrupt 2 control 00: wake-up interrupt 2 disabled 01: wake-up interrupt 2 on rising edge 10: wake-up interrupt 2 on falling edge 11: wake-up interrupt 2 on both edges 3 STBCC R/W 0 CAN standby control 0: When the SBC is in Normal mode (MC = 1x): CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared regardless of V2 output voltage. When the SBC is in Standby/Sleep mode (MC = 0x): CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up interrupts cannot be requested. 1: CAN is in Lowpower mode with bus wake-up detection enabled, regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be requested. 2 RTHC R/W 0 reset threshold control 0: The reset threshold is set to the 90 % V1 undervoltage detection voltage (Vuvd; see Table 10) 1: The reset threshold is set to the 70 % V1 undervoltage detection voltage (Vuvd; see Table 10) 1 WSE1 R/W 0 WAKE1 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) A2, A1, A0 R RO UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 13 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 6. Bit 0 Int_Control register Symbol WSE2 Access Power-on default R/W 0 Description WAKE2 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) 6.2.6 Int_Status register Table 7. Bit 15:13 12 Int_Status register[1] Symbol Access Power-on default 011 0 R/W Description register address access status 0: register set to read/write 1: register set to read only 11 V1UI R/W 0 V1 undervoltage interrupts 0: no V1 undervoltage warning interrupt pending 1: V1 undervoltage warning interrupt pending 10 V2UI R/W 0 V2 undervoltage interrupts 0: no V2 undervoltage warning interrupt pending 1: V2 undervoltage warning interrupt pending 9:8 7 reserved CI R R/W 00 0 cyclic interrupt 0: no cyclic interrupt pending 1: cyclic interrupt pending 6 WI1 R/W 0 wake-up interrupt 1 0: no wake-up interrupt 1 pending 1: wake-up interrupt 1 pending 5 POSI R/W 1 power-on status interrupt 0: no power-on interrupt pending 1: power-on interrupt pending 4 WI2 R/W 0 wake-up interrupt 2 0: no wake-up interrupt 2 pending 1: wake-up interrupt 2 pending 3 CWI R/W 0 CAN wake-up interrupt 0: no CAN wake-up interrupt pending 1: CAN wake-up interrupt pending 2:0 [1] A2, A1, A0 R RO reserved R 000 An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 14 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.3 On-chip oscillator The on-chip oscillator provides the timing reference for the on-chip watchdog and the internal timers. The on-chip oscillator is supplied by an internal supply that is connected to VBAT and is independent of V1/V2. 6.4 Watchdog (UJA1076/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4). The default watchdog period is 128 ms. A watchdog trigger event is any write access to the WD_and_Status register. When the watchdog is triggered, the watchdog timer is reset. In watchdog Window mode, a watchdog trigger event within a closed watchdog window (i.e. the first half of the window before ttrig(wd)1) will generate an SBC reset. If the watchdog is triggered before the watchdog timer overflows in Timeout or Window mode, or within the open watchdog window (after ttrig(wd)1 but before ttrig(wd)2), the timer restarts immediately. The following watchdog events result in an immediate system reset: * * * * * the watchdog overflows in Window mode the watchdog is triggered in the first half of the watchdog period in Window mode the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending the state of the WDOFF pin changes in Normal mode or Standby mode the watchdog mode control bit (WMC) changes state in Normal mode After a watchdog reset (short reset; see Section 6.5.1 and Table 11), the default watchdog period is selected (NWP = 100). The watchdog can be switched off completely by forcing pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will re-enable it. Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is pending. Any attempt to change WMC when an interrupt is pending will be ignored. 6.4.1 Watchdog Window behavior The watchdog runs continuously in Window mode. If the watchdog overflows, or is triggered in the first half of the watchdog period (less than ttrig(wd)1 after the start of the watchdog period), a system reset will be performed. Watchdog overflow occurs if the watchdog is not triggered within ttrig(wd)2 after the start of watchdog period. If the watchdog is triggered in the second half of the watchdog period (at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the watchdog period), the watchdog will be reset. The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode and the watchdog mode control bit (WMC) is set to 0. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 15 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.4.2 Watchdog Timeout behavior The watchdog runs continuously in Timeout mode. It can be reset at any time by a watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set. If a CI is already pending, a system reset is performed. The watchdog is in Timeout mode when pin WDOFF is LOW and: * the SBC is in Standby mode and bit WMC = 0 or * the SBC is in Normal mode and bit WMC = 1 6.4.3 Watchdog Off behavior The watchdog is disabled in this state. The watchdog is in Off mode when: * the SBC is in Off, Overtemp or Sleep modes * the SBC is in Standby mode and bit WMC = 1 * the SBC is in any mode and the WDOFF pin is HIGH 6.5 System reset The following events will cause the SBC to perform a system reset: * V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN pin) * * * * * * * * An external reset (RSTN forced LOW) Watchdog overflow (Window mode) Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending Watchdog triggered too early in Window mode WMC value changed in Normal mode WDOFF pin state changed SBC goes to Sleep mode (MC set to 01; see Table 5) while INTN is driven LOW SBC goes to Sleep mode (MC set to 01; see Table 5) while STBCC = WIC1 = WIC2 = 0 * SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending * Software reset (SWR = 1) * SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor on RSTN pin) A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already pending. The UJA1076 provides three signals for dealing with reset events: * RSTN input/output for performing a global ECU system reset or forcing an external reset * EN pin, a fail-safe global enable output * LIMP pin, a fail-safe limp home output UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 16 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.5.1 RSTN pin A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least tfltr by the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a system reset is triggered internally. The reset pulse width (tw(rst)) is selectable (short or long) if the system reset was generated by a V1 undervoltage event (see Section 6.6.2) or by the SBC leaving Off (VBAT > Vth(det)pon) or Overtemp (temperature < Tth(rel)otp) modes. A short reset pulse is selected by connecting a 900 10 % resistor between pins RSTN and V1. If a resistor is not connected, the reset pulse will be long (see Table 11). In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short. 6.5.2 EN output The EN pin can be used to control external hardware, such as power components, or as a general-purpose output when the system is running properly. In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in the Mode_Control register; see Table 5) via the SPI interface. Pin EN will be HIGH when ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior is illustrated in Figure 5. mode STANDBY NORMAL STANDBY ENC EN RSTN 015aaa074 Fig 5. Behavior of EN pin 6.5.3 LIMP output The LIMP pin can be used to enable the so called `limp home' hardware in the event of an ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, RSTN or V1 clamped LOW and user-initiated or external reset events. The LIMP pin is a battery-related, active-LOW, open-drain output. A system reset will cause the limp home warning control bit (bit LHWC in the Mode_Control register; see Table 5) to be set. If LHWC is already set when the system reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application should clear LHWC after each reset event to ensure the LIMP output is not activated during normal operation. In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always active. If the application manages to recover from the event that activated the LIMP output, LHC can be cleared to deactivate the LIMP output. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 17 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4.5 V to 28 V. The SBC can handle maximum voltages up to 40 V. If the voltage on pin BAT falls below the power-off detection threshold (Vth(det)poff), the SBC immediately enters Off mode, which means that the voltage regulators and the internal logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage rises above the power-on detection threshold, Vth(det)pon. The POSI bit in the Int_Status register is set to 1 when the SBC leaves Off mode. 6.6.2 Voltage regulator V1 Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V (depending on the UJA1076 version). To prevent the device overheating at high ambient temperatures or high average currents, an external PNP transistor can be connected as illustrated in Figure 6. In this configuration, the power dissipation is distributed between the SBC and the PNP transistor. Bit PDC in the Mode_Control register (Table 5) is used to regulate how the power dissipation is distributed - if PDC = 0, the PNP transistor will be activated when the load current reaches 85 mA (50 mA if PDC = 1) at Tvj = 150 C. V1 will continue to deliver 85 mA while the transistor delivers the additional load current (see Figure 7 and Figure 8). battery VEXCTRL VEXCC UJA107x BAT V1 015aaa098 Fig 6. External PNP transistor control circuit UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 18 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 250 mA 215 mA 85 mA load current 50 mA Ith(act)PNP = 85 mA (PDC = 0) IV1 165 mA Ith(deact)PNP = 50 mA (PDC = 0) PNP current 015aaa111 Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0) Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor, up to its current limit. If the load current continues to rise, IV1 will increase above the selected PDC threshold (to a maximum of 250 mA). For a fast ramping load current, V1 will deliver the required load current (to a maximum of 250 mA) until the PNP transistor has switched on. Once the transistor has been activated, V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load current (see Figure 8). 250 mA load current 250 mA Ith(act)PNP = 85 mA (PDC = 0) IV1 0 mA -165 mA 165 mA PNP current 015aaa075 Fig 8. V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0) UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 19 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip For short-circuit protection, a resistor needs to be connected between pins V1 and VEXCC to allow the current to be monitored. This resistor limits the current delivered by the external transistor. If the voltage difference between pins VEXCC and V1 reaches Vth(act)Ilim, the PNP current limiting activation threshold voltage, the transistor current will not increase further. The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor () of between 60 and 500 can be used. If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin VEXCTRL can be left open. One advantage of this scalable voltage regulator concept is that there are no PCB layout restrictions when using the external PNP. The distance between the UJA1076 and the external PNP doesn't affect the stability of the regulator loop because the loop is realized within the UJA1076. Therefore, it is recommended that the distance between the UJA1076 and PNP transistor be maximized for optimal thermal distribution. The output voltage on V1 is monitored continuously and a system reset signal is generated if an undervoltage event occurs. A system reset is generated if the voltage on V1 falls below the undervoltage detection voltage (Vuvd; see Table 10). The reset threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit (RTHC) in the Int_Control register (Table 6). In addition, an undervoltage warning (a V1UI interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be read via bit V1S in the WD_and_Status register (Table 4). 6.6.3 Voltage regulator V2 Voltage regulator V2 is reserved for the high-speed CAN transceiver, providing a 5 V supply. V2 can be activated and deactivated via the MC bits in the Mode_Control register (Table 5). An undervoltage warning (a V2UI interrupt) is generated when the output voltage drops below 90 % of its nominal value. The status of V2 can be read via bit V2S in the WD_and_Status register (Table 4) in Normal mode (V2S = 1 in all other modes). V2 can be deactivated (MC = 10) to allow the internal CAN transceiver to be supplied from an external source or from V1. The alternative voltage source must be connected to pin V2. All internal functions (e.g. undervoltage protection) will work normally. 6.7 CAN transceiver The analog section of the UJA1076 CAN transceiver corresponds to that integrated into the TJA1042/TJA1043. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the automotive industry, providing differential transmit and receive capability to a CAN protocol controller. 6.7.1 CAN operating modes 6.7.1.1 Active mode The CAN transceiver is in Active mode when: UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 20 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip * the SBC is in Normal mode (MC = 10 or 11) * the transceiver is enabled (bit STBCC = 0; see Table 6) and * V2 is enabled and its output voltage is above its undervoltage threshold, Vuvd or * V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its undervoltage threshold (see Section 6.6.3) In CAN Active mode, the transceiver can transmit and receive data via the CANH and CANL pins. The differential receiver converts the analog data on the bus lines into digital data which is output on pin RXDC. The transmitter converts digital data generated by a CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus lines. 6.7.1.2 Lowpower/Off modes The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit STBCC = 1 (see Table 6). The CAN transceiver can be woken up remotely via pins CANH and CANL in Lowpower mode. When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in Off mode to minimize quiescent current consumption. A filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or EMI. A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up filter and trigger a wake-up event (see Figure 9; note that additional pulses may occur between the recessive/dominant phases). The minimum recessive/dominant bus times for CAN transceiver wake-up (twake(busrec)min and twake(busdom)min) must be satisfied (see Table 11). recessive wake-up dominant recessive dominant twake < tto(wake) 015aaa107 Fig 9. CAN wake-up timing diagram UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 21 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.7.2 Split circuit Pin SPLIT provides a DC stabilized voltage of 0.5VV2. It is activated in CAN Active mode only. Pin SPLIT is floating in CAN Lowpower and Off modes. The VSPLIT circuit can be used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the center tap of the split termination (see Figure 10). A transceiver in the network that is not supplied and that generates a significant leakage current from the bus lines to ground, can result in a recessive bus voltage of < 0.5VV2. In this event, the split circuit will stabilize the recessive voltage at 0.5VV2. So a start of transmission will not generate a step in the common-mode signal which would lead to poor ElectroMagnetic Emission (EME) performance. V2 UJA1076 CANH R 60 VSPLIT = 0.5 VCC in normal mode; otherwise floating R SPLIT 60 CANL GND 015aaa121 Fig 10. Stabilization circuitry and application using the SPLIT pin 6.7.3 Fail-safe features 6.7.3.1 TXDC dominant time-out function A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW state on pin TXDC persists for longer than the TXDC dominant time-out time (tto(dom)TXDC), the transmitter will be disabled, releasing the bus lines to recessive state. This function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). The TXDC dominant time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time also defines the minimum possible bit rate of 10 kbit/s. 6.7.3.2 Pull-up on TXDC pin Pin TXDC has an internal pull-up towards VV1 to ensure a safe defined state in case the pin is left floating. 6.8 Local wake-up input The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity (falling, rising or both) of the wake-up pins can be configured independently via the WIC1 and WIC2 bits in the Int_Control register Table 6). These bits can also be used to disable wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 22 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and enter Standby mode. The status of the wake-up pins can be read via the wake-up level status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4). Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts is enabled (WIC1 00 or WIC2 00). enable bias WBIASI (internal) disable bias WBIAS pin WAKEx pin Wake-up int disable bias wake level latched 015aaa078 Fig 11. Wake-up pin sampling synchronized with WBIAS signal The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are sampled continuously). The sampling will be performed on the rising edge of WBIAS (see Figure 11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit (WBC) in the Mode_Control register. Figure 12 shows typical circuit for implementing cyclic sampling of the wake-up inputs. UJA1076 BAT 47 k PDTA144E WBIAS 47 k biasing of switches WAKE1 t WAKE2 sample of WAKEx sample of WAKEx sample of WAKEx GND 015aaa122 Fig 12. Typical application for cyclic sampling of wake-up signals UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 23 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 6.9 Interrupt output Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit in the Int_Status register (Table 7). Clearing bit CWI in Standby mode only clears the interrupt status bit and not the pending wake-up. The pending wake-up is cleared on entering Normal mode and when the corresponding standby control bit (STBCC) is 0. On devices that contain a watchdog, the Cyclic Interrupt (CI) is enabled when the watchdog switches to Timeout mode while the SBC is in Standby mode or Normal mode (provided WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode. The CI is provided to alert the microcontroller when the watchdog overflows in Timeout mode. The CI will wake up the microcontroller from a C standby mode. After polling the Int_Status register, the microcontroller will be aware that the application is in cyclic wake up mode. It can then perform some checks on CAN before returning to the C standby mode. 6.10 Temperature protection The temperature of the SBC chip is monitored in Normal and Standby modes. If the temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven LOW and limp home is activated. In addition, the voltage regulators and the CAN transmitter are switched off (see also Section 6.1.6 "Overtemp mode"). When the temperature falls below the temperature shutdown threshold, the SBC will go to Standby mode. The temperature shutdown threshold is between 165 C and 200 C. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 24 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vx Parameter voltage on pin x Conditions DC value pins V1, V2 and INTN pins TXDC, RXDC, EN, SDI, SDO, SCK, SCSN, RSTN and WDOFF pin VEXCC pins WAKE1, WAKE2 and WBIAS; with respect to any other pin pin LIMP and BAT pin VEXCTRL pins CANH, CANL and SPLIT; with respect to any other pin IR(V1-BAT) Vtrt reverse current from VV1 5 V pin V1 to pin BAT transient voltage on pins BAT: via reverse polarity diode/capacitor CANL, CANH, SPLIT: coupling with two capacitors on the bus lines VESD electrostatic discharge voltage IEC 61000-4-2 pins BAT with capacitor, CANH and CANL; via a series resistor on pins SPLIT, WAKE1 and WAKE2 HBM pins CANH, CANL, SPLIT, WAKE1 and WAKE2 pin BAT; referenced to ground pin TEST2; referenced to pin BAT pin TEST2; referenced to other reference pins any other pin MM any pin CDM corner pins any other pin Tvj Tstg virtual junction temperature storage temperature [9] [8] [7] [3] [4] [1] Min -0.3 -0.3 VV1 - 0.3 -58 -0.3 -0.3 -58 -150 Max 7 VV1 + 0.3 Unit V V VV1 + 0.35 V +58 +40 VBAT + 0.3 +58 250 +100 V V V V mA V [2] -6 +6 kV [5] [6] -8 -4 -1.25 -2 -2 -300 -750 -500 -40 -55 +8 +4 +2 +2 +2 +300 +750 +500 +150 +150 kV kV kV kV kV V V V C C UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 25 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 8. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Tamb Parameter ambient temperature Conditions Min -40 Max +125 Unit C [1] [2] [3] [4] [5] [6] [7] [8] [9] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-). Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. IEC 61000-4-2 (150 pF, 330 ). ESD performance according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house for pins BAT, CANH, CANL, WAKE1 and WAKE2. The result is equal to or better than 6 kV. Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). V1, V2 and BAT connected to GND, emulating application circuit. Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ). Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF). In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P x Rth(vj-a), where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 26 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 8. Thermal characteristics optional heatsink top layer PCB copper area: (bottom layer) 2 cm2 optional heatsink top layer optional heatsink top layer PCB copper area: (bottom layer) 8 cm2 015aaa137 Layout conditions for Rth(j-a) measurements: board finish thickness 1.6 mm 10 %, double-layer board, board dimensions 129 mm x 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm 0.08 mm, Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm x 25 mm will reduce thermal resistance (see Figure 14). Fig 13. HTSSOP PCB UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 27 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 90 Rth(j-a) (K/W) 70 015aaa138 without heatsink top layer 50 with heatsink top layer 30 0 2 4 6 8 PCB Cu heatsink area (cm2) 10 Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper area Table 9. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions single-layer board four-layer board [1] [2] Typ 78 39 Unit K/W K/W [1] [2] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 28 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 9. Static characteristics Table 10. Static characteristics Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol VBAT IBAT Parameter battery supply voltage battery supply current MC = 00 (Standby; V1 on, V2 off) STBCC = 1 (CAN wake-up enabled) WIC1 = WIC2 = 11 (WAKE interrupts enabled); 7.5 V < VBAT < 28 V IV1 = 0 mA; VRSTN = VSCSN = VV1 VTXDC = VV1; VSDI = VSCK = 0 V Tvj = -40 C Tvj = 25 C Tvj = 150 C MC = 01 (Sleep; V1 off, V2 off) STBCC = 1 (CAN wake-up enabled) WIC1 = WIC2 = 11 (WAKE interrupts enabled); 7.5 V < VBAT < 28 V; VV1 = 0 V Tvj = -40 C Tvj = 25 C Tvj = 150 C contributed by CAN wake-up receiver STBCC = 1; VCANH = VCANL = 2.5 V 5.5 V < VBAT < 28 V contributed by WAKE pin edge detectors; WIC1 = WIC2 = 11 VWAKE1 = VWAKE2 =VBAT IBAT(add) additional battery supply current 5.1 V < VBAT < 7.5 V 4.5 V < VBAT < 5.1 V V1 on (5 V version) V2 on; MC = 11 V2UIE = 1; IV2 = 0 mA CAN Active mode (recessive) STBCC = 0; MC = 1x; VTXDC = VV1 ICANH = ICANL = 0 mA 5.5 V < VBAT < 28 V CAN active (dominant) STBCC = 0; MC = 1x; VTXDC = 0 V R(CANH-CANL) = 45 5.5 V < VBAT < 28 V Vth(det)pon Vth(det)poff Vhys(det)pon UJA1076_2 Conditions Min 4.5 Typ - Max 28 Unit V Supply; pin BAT - 82 75 67 97 87 79 A A A 1 59 55 50 6 70 64 57 13 A A A A 0 5 10 A 100 - - 50 3 950 10 A mA A mA - - 70 mA power-on detection threshold voltage power-off detection threshold voltage power-on detection hysteresis voltage All information provided in this document is subject to legal disclaimers. 4.5 4.25 200 - 5.5 4.5 - V V mV (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 29 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 10. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Vuvd(ctrl)Iext Parameter external current control undervoltage detection voltage output voltage VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V IV1 = -200 mA to -5 mA VO(V1)nom = 5 V; VBAT = 5.5 V to 28 V IV1 = -250 mA to -200 mA VO(V1)nom = 5 V; VBAT = 5.5 V to 5.75 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C VO(V1)nom = 5 V; VBAT = 5.75 V to 28 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V IV1 = -250 mA to -5 mA VO(V1)nom = 3.3 V; VBAT = 4.5 V to 28 V IV1 = -250 mA to -5 mA 150 C < Tvj < 200 C R(BAT-V1) resistance between pin BAT and pin V1 undervoltage detection voltage VO(V1)nom = 5 V; VBAT = 4.5 V to 5.5 V IV1 = -250 mA to -5 mA regulator in saturation 90 %; VO(V1)nom = 5 V; RTHC = 0 90 %; VO(V1)nom = 3.3 V; RTHC = 0 70 %; VO(V1)nom = 5 V; RTHC = 1 Vuvr IO(sc) VV1 undervoltage recovery voltage short-circuit output current voltage variation on pin V1 90 %; VO(V1)nom = 5 V 90 %; VO(V1)nom = 3.3 V IVEXCC = 0 mA as a function of load current variation VBAT = 5.75 V to 28 V IV1 = -250 mA to -5 mA as a function of supply voltage variation VBAT = 5.5 V to 28 V; IV1 = -30 mA VVEXCTRL 4.5 V; VBAT = 6 V to 28 V 4.5 2.97 3.5 4.56 3.025 -600 4.75 3.135 3.75 4.9 3.234 -250 25 V V V V V mA mV 3 2.97 3.3 3.366 V 3.234 3.3 3.366 V 4.85 5 5.1 V 4.5 5 5.1 V 4.75 5 5.1 V Conditions Min 5.9 Typ Max 7.5 Unit V Voltage source; pin V1 VO 4.9 5 5.1 V Vuvd Load regulation Line regulation VV1 voltage variation on pin V1 25 mV PNP base; pin VEXCTRL IO(sc) short-circuit output current 3.5 5.8 8 mA UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 30 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 10. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Ith(act)PNP Parameter PNP activation threshold current Conditions load current increasing; external PNP transistor connected - see Section 6.6.2 PDC 0 PDC 0; Tvj = 150 C PDC 1 PDC 1; Tvj = 150 C Ith(deact)PNP PNP deactivation threshold current load current falling; external PNP transistor connected - see Section 6.6.2 PDC 0 PDC 0; Tvj = 150 C PDC 1 PDC 1; Tvj = 150 C PNP collector; pin VEXCC Vth(act)Ilim current limiting activation threshold voltage measured across resistor connected between pins VEXCC and V1 (see Section 6.6.2) 2.97 V VV1 5.5 V 6 V < VBAT < 28 V VBAT = 5.5 V to 28 V IV2 = -100 mA to 0 mA VBAT = 6 V to 28 V IV2 = -120 mA to 0 mA VV2 voltage variation on pin V2 as a function of supply voltage variation VBAT = 5.5 V to 28 V IV2 = -10 mA as a function of load current variation; 6 V < VBAT < 28 V IV2 = -100 mA to -5 mA Vuvd Vuvr Vuvhys IO(sc) Vth(sw) Vhys(i) Rpd(SCK) Rpu(SCSN) undervoltage detection voltage undervoltage recovery voltage undervoltage hysteresis voltage short-circuit output current switching threshold voltage input hysteresis voltage pull-down resistance on pin SCK pull-up resistance on pin SCSN VV2 = 0 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V 240 330 mV 40 44 11 12 76 50 22 15 120 59 36 18 mA mA mA mA 74 74 44 44 130 85 76 50 191 99 114 59 mA mA mA mA Min Typ Max Unit Voltage source; pin V2 VO output voltage 4.75 4.75 5 5 5.25 5.25 60 V V mV - - 80 mV 4.5 4.55 20 -250 - 4.70 4.75 80 -100 0.7VV1 900 400 400 V V mV mA V mV k k Serial peripheral interface inputs; pins SDI, SCK and SCSN 0.3VV1 100 50 50 130 130 UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 31 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 10. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol ILI(SDI) Parameter input leakage current on pin SDI HIGH-level output current LOW-level output current output leakage current VSCSN = 0 V; VO = VV1 - 0.4 V VV1 = 2.97 V to 5.5 V VSCSN = 0 V; VO = 0.4 V VV1 = 2.97 V to 5.5 V VSCSN = VV1; VO = 0 V to VV1 VV1 = 2.97 V to 5.5 V VRSTN = 0.8VV1 VV1 = 2.97 V to 5.5 V strong; VRSTN = 0.2VV1 VV1 = 2.97 V to 5.5 V -40 C < Tvj < 200 C weak; VRSTN = 0.8VV1 VV1 = 2.97 V to 5.5 V -40 C < Tvj < 200 C VOL LOW-level output voltage VV1 = 1 V to 5.5 V pull-up resistor to VV1 900 -40 C < Tvj < 200 C; VBAT < 28 V VV1 = 2.975 V to 5.5 V pull-up resistor to V1 900 -40 C < Tvj < 200 C VOH Vth(sw) Vhys(i) IOL IOH IOL VOL Vth(sw) Vhys(i) Rpupd Vth(sw) Vhys(i) Ipu UJA1076_2 Conditions Min -5 Typ - Max +5 Unit A Serial peripheral interface data output; pin SDO IOH IOL ILO -30 1.6 -5 -1.6 30 5 mA mA A Reset output with clamping detection; pin RSTN IOH IOL HIGH-level output current LOW-level output current -1500 4.9 -100 40 A mA 200 - 540 A 0 - 0.2VV1 V 0 - 0.5 V HIGH-level output voltage switching threshold voltage input hysteresis voltage LOW-level output current HIGH-level output current LOW-level output current LOW-level output voltage switching threshold voltage input hysteresis voltage pull-up/pull-down resistance switching threshold voltage input hysteresis voltage pull-up current -40 C < Tvj < 200 C VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VOL = 0.4 V VOH = VV1 - 0. 4 V VV1 = 2.97 V to 5.5 V VOL = 0.4 V; VV1 = 2.97 V to 5.5 V IOL = 20 A; VV1 = 1.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V 0.8VV1 0.3VV1 100 1.6 -20 1.6 - VV1 + 0.3 0.7VV1 900 15 -1.6 20 0.4 0.7VV1 900 20 3.75 1000 0 V V mV mA mA mA V V mV k V mV A Interrupt output; pin INTN Enable output; pin EN Watchdog off input; pin WDOFF 0.3VV1 100 5 2 100 VWAKE = 0 V for t < twake All information provided in this document is subject to legal disclaimers. 10 - Wake input; pin WAKE1, WAKE2 -2 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 32 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 10. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Ipd IO Parameter pull-down current output current Conditions VWAKE = VBAT for t < twake VLIMP = 0.4 V; LHC = 1 Tvj = -40 C to 200 C VWBIAS = 1.4 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V Min 0 0.8 Typ Max 2 8 Unit A mA Limp home output; pin LIMP Wake bias output; pin WBIAS IO Vth(sw) Vhys(i) Rpu IOH IOL Rpu VO(dom) output current switching threshold voltage input hysteresis voltage pull-up resistance HIGH-level output current LOW-level output current pull-up resistance dominant output voltage CAN Active mode VRXDC = VV1 - 0.4 V VRXDC = 0.4 V MC = 00; Standby mode CAN Active mode VV2 = 4.5 V to 5.5 V; VTXDC = 0 V R(CANH-CANL) = 60 pin CANH pin CANL Vdom(TX)sym VO(dif)bus transmitter dominant voltage symmetry Vdom(TX)sym = VV2 - VCANH - VCANL R(CANH-CANL) = 60 2.75 0.5 -400 1.5 3.5 1.5 4.5 2.25 400 3.0 V V mV V 1 7 0.7VV1 900 25 -1.5 20 25 mA V mV k mA mA k CAN transmit data input; pin TXDC 0.3VV1 100 4 -20 1.6 4 12 12 CAN receive data output; pin RXDC High-speed CAN bus lines; pins CANH and CANL bus differential output voltage CAN Active mode (dominant) VV2 = 4.75 V to 5.25 V; VTXDC = 0 V R(CANH-CANL) = 45 to 65 CAN Active mode (recessive) VV2 = 4.5 V to 5.5 V; VTXDC = VV1 R(CANH-CANL) = no load -50 0 +50 mV VO(rec) recessive output voltage CAN Active mode; VV2 = 4.5 V to 5.5 V VTXDC = VV1 R(CANH-CANL) = no load CAN Lowpower/Off mode R(CANH-CANL) = no load 2 0.5VV2 3 V -0.1 - 0.1 V IO(dom) dominant output current CAN Active mode VTXDC = 0 V; VV2 = 5 V pin CANH; VCANH = 0 V pin CANL; VCANL = 40 V -100 40 -3 -70 70 -40 100 3 mA mA mA IO(rec) recessive output current VCANL = VCANH = -27 V to 32 V VTXDC = VV1; VV2 = 4.5 V to 5.5 V UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 33 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 10. Static characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Vth(RX)dif Parameter Conditions Min 0.5 Typ 0.7 Max 0.9 Unit V differential receiver threshold CAN Active mode voltage VV2 = 4.5 V to 5.5 V -30 V < VCANH < 30 V -30 V < VCANL < 30 V CAN Lowpower mode -12 V < VCANH < 12 V -12 V < VCANL < 12 V Vhys(RX)dif differential receiver hysteresis voltage CAN Active mode VV2 = 4.5 V to 5.5 V -30 V < VCANH < 30 V -30 V < VCANL < 30 V CAN Active mode; VV2 = 5 V VCANH = VCANL = 5 V CAN Active mode; VV2 = 5 V VCANH = VCANL = 5 V CAN Active mode; VV2 = 5.5 V VCANH = VCANL = -35 V to +35 V CAN Active mode; not tested CAN Active mode; not tested VBAT = 0 V; VV2 = 0 V VCANH = VCANL = 5 V CAN Active mode VV2 = 4.5 V to 5.5 V ISPLIT = -500 A to 500 A CAN Active mode VV2 = 4.5 V to 5.5 V; RL 1 M IL leakage current CAN Lowpower/Off mode or Active mode with VV2 < 4.5 V VSPLIT = -30 V to + 30 V 0.4 0.7 1.15 V 40 120 400 mV Ri(cm) Ri Ri(dif) Ci(cm) Ci(dif) ILI common-mode input resistance input resistance deviation differential input resistance common-mode input capacitance differential input capacitance input leakage current 9 -1 19 -5 15 30 - 28 +1 52 20 10 +5 k % k pF pF A CAN bus common mode stabilization output; pin SPLIT VO output voltage 0.3VV2 0.5VV2 0.7VV2 V 0.45 x VV2 -5 0.5 x VV2 - 0.55 x VV2 +5 V A Temperature protection Tth(act)otp overtemperature protection activation threshold temperature overtemperature protection release threshold temperature 165 180 200 C Tth(rel)otp 126 138 150 C UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 34 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 10. Dynamic characteristics Table 11. Dynamic characteristics Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol td(uvd) tdet(CL)L Parameter undervoltage detection delay time Conditions VV1 falling; dVV1/dt = 0.1 V/s Min 7 95 Typ Max 23 140 Unit s ms Voltage source; pin V1 LOW-level clamping detection VV1 < 0.9VO(V1)nom; V1 active time undervoltage detection delay time clock cycle time SPI enable lead time SPI enable lag time clock HIGH time clock LOW time data input set-up time data input hold time data output valid time chip select pulse width HIGH reset pulse width VV2 falling, dVV2/dt = 0.1 V/us Voltage source; pin V2 td(uvd) 7 23 s Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO tcy(clk) tSPILEAD tSPILAG tclk(H) tclk(L) tsu(D) th(D) tv(Q) tWH(S) tw(rst) tdet(CL)L tfltr tfltr twake td(po) td(TXDCH-RXDCH) VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select falls VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select rises VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V VV1 = 2.97 V to 5.5 V pin SDO; VV1 = 2.97 V to 5.5 V CL = 100 pF VV1 = 2.97 V to 5.5 V long; Ipu(RSTN) < 100 A; no pull-up short; Rpu(RSTN) = 900 to 1100 LOW-level clamping detection RSTN driven HIGH internally but time RSTN remains LOW filter time filter time wake-up time power-on delay time delay time from TXDC HIGH to RXDC HIGH 50 % VTXDC to 50 % VRXDC VV2 = 4.5 V to 5.5 V R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF; CRXDC = 15 pF fTXDC = 250 kHz 320 110 140 160 160 0 80 20 20 3.6 95 7 0.9 10 113 60 110 25 5 140 18 2.3 40 278 235 ns ns ns ns ns ns ns ns ns ms ms ms s ms s s ns Reset output; pin RSTN Watchdog off input; pin WDOFF Wake input; pin WAKE1, WAKE2 CAN transceiver timing; pins CANH, CANL, TXDC and RXDC UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 35 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 11. Dynamic characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol td(TXDCL-RXDCL) Parameter delay time from TXDC LOW to RXDC LOW Conditions 50 % VTXDC to 50 % VRXDC VV2 = 4.5 V to 5.5 V R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF CRXDC =15 pF; fTXDC = 250 kHz VV2 = 4.5 V to 5. 5 V R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF VV2 = 4.5 V to 5.5 V R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF Min 60 Typ Max 235 Unit ns td(TXDC-busdom) delay time from TXDC to bus dominant delay time from TXDC to bus recessive - 70 - ns td(TXDC-busrec) - 90 - ns td(busdom-RXDC) delay time from bus dominant VV2 = 4.5 V to 5.5 V to RXDC R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF CRXDC = 15 pF delay time from bus recessive VV2 = 4.5 V to 5.5 V to RXDC R(CANH-CANL) = 60 C(CANH-CANL) = 100 pF CRXDC = 15 pF minimum bus dominant wake-up time first pulse (after first recessive) for wake-up on pins CANH and CANL Sleep mode second pulse for wake-up on pins CANH and CANL - 75 - ns td(busrec-RXDC) - 95 - ns twake(busdom)min 0.5 - 3 s 0.5 0.5 0.5 0.4 1.8 - 3 3 3 1.2 4.5 s s s ms ms twake(busrec)min minimum bus recessive wake-up time first pulse for wake-up on pins CANH and CANL; Sleep mode second pulse (after first dominant) for wake-up on pins CANH and CANL tto(wake) tto(dom)TXDC wake-up time-out time between wake-up and confirm messages; Sleep mode TXDC dominant time-out time CAN online; VV2 = 4.5 V to 5.5 V VTXDC = 0 V WBIAS LOW time cycle time WBC = 1 WBC = 0 Wake bias output; pin WBIAS tWBIASL tcy Watchdog ttrig(wd)1 ttrig(wd)2 watchdog trigger time 1 watchdog trigger time 2 Normal mode watchdog Window mode only Normal, Standby and Sleep modes watchdog Window mode only [1] 227 58.1 14.5 - 278 71.2 17.8 0.555 x NWP[2] 1.11 x NWP[2] s ms ms ms ms 0.45 x NWP[2] 0.9 x NWP[2] [3] UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 36 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Table 11. Dynamic characteristics ...continued Tvj = -40 C to +150 C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 to 65 ; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Oscillator fosc [1] [2] [3] Parameter oscillator frequency Conditions Min 460.8 Typ 512 Max 563.2 Unit kHz A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog Window mode only. The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than ttrig(wd)2 after the start of the watchdog period (watchdog overflows). BAT RXDC CRXDC CANH SBC TXDC GND CANL RCANH - RCANL CCANH - CCANL 015aaa079 Fig 15. Timing test circuit for CAN transceiver UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 37 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip HIGH TXDC LOW CANH CANL dominant 0.9 V VO(dif)bus 0.5 V recessive HIGH RXDC LOW td(TXDC-busdom) td(TXDC-busrec) td(busdom-RXDC) td(TXDCL-RXDCL) td(TXDCH-RXDCH) td(busrec-RXDC) 015aaa151 Fig 16. CAN transceiver timing diagram SCS tSPILEAD Tcy(clk) tclk(H) tclk(L) tSPILAG tWH(S) SCK tsu(D) th(D) SDI X MSB tv(Q) LSB X floating SDO X MSB LSB floating 015aaa045 Fig 17. SPI timing diagram UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 38 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 39 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 D E A X c y exposed die pad side HE vMA Z Dh 32 17 Eh pin 1 index A2 A1 (A3) A Lp L 1 e bp 16 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.1 10.9 Dh 5.1 4.9 E(2) 6.2 6.0 Eh 3.6 3.4 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-11-02 Fig 18. Package outline SOT549-1 (HTSSOP32) UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 40 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 41 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 13.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 42 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 43 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 14. Revision history Table 14. Revision history Release date 20100527 Data sheet status Product data sheet Change notice Supersedes UJA1076_1 Document ID UJA1076_2 Modifications: * * * * * * * * Template upgraded to Rev. 2.11 including revised legal information Figure 16: revised Table 4: bit 7: WOS revised Table 8: revised values/conditions - VESD, IR(V1-BAT) Table 9: added Table 10: revised parameter values/conditions - IO for LIMP pin; R(BAT-V1); Vuvr for pin V1, VOL for RSTN pin Table 11: revised parameter values/conditions - tdet(CL)L for RSTN pin Section 6.7.1.2, Table 11: parameters renamed to twake(busdom)min, twake(busrec)min Product data sheet - UJA1076_1 20091125 UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 44 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 45 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UJA1076_2 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 -- 27 May 2010 46 of 47 NXP Semiconductors UJA1076 High-speed CAN core system basis chip 17. Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 6.4 6.4.1 6.4.2 6.4.3 6.5 6.5.1 6.5.2 6.5.3 6.6 6.6.1 6.6.2 6.6.3 6.7 6.7.1 6.7.1.1 6.7.1.2 6.7.2 6.7.3 6.7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 2 Control and Diagnostic features . . . . . . . . . . . . 3 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 System Controller . . . . . . . . . . . . . . . . . . . . . . 7 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 10 WD_and_Status register. . . . . . . . . . . . . . . . . 11 Mode_Control register . . . . . . . . . . . . . . . . . . 12 Int_Control register . . . . . . . . . . . . . . . . . . . . . 13 Int_Status register. . . . . . . . . . . . . . . . . . . . . . 14 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 15 Watchdog (UJA1076/xx/WD versions) . . . . . . 15 Watchdog Window behavior . . . . . . . . . . . . . . 15 Watchdog Timeout behavior . . . . . . . . . . . . . . 16 Watchdog Off behavior . . . . . . . . . . . . . . . . . . 16 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 16 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 18 Battery pin (BAT) . . . . . . . . . . . . . . . . . . . . . . 18 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 18 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . 20 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 20 CAN operating modes . . . . . . . . . . . . . . . . . . 20 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Lowpower/Off modes . . . . . . . . . . . . . . . . . . . 21 Split circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 22 TXDC dominant time-out function. . . . . . . . . . 22 6.7.3.2 6.8 6.9 6.10 7 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Pull-up on TXDC pin . . . . . . . . . . . . . . . . . . . Local wake-up input . . . . . . . . . . . . . . . . . . . . Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . Temperature protection . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 24 24 25 27 29 35 39 39 40 41 41 41 41 42 44 45 45 45 45 46 46 47 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 May 2010 Document identifier: UJA1076_2 |
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